View USB84604_8676608.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2014-2016 microchip technology inc. ds60001295c-page 1 highlights ? controller hub ic with 4 downstream ports ? high-speed inter-chip (hsic) support - upstream port selectable between hsic or usb 2.0 ? usb-if battery charger revision 1.2 support on downstream ports (dcp, cdp, sdp) ? battery charging support for apple ? devices ? flexconnect : downstream port 1 able to swap with upstream port, allowing master capable devices to control other devices on the hub ? usb to i 2 c tm /spi/gpio/uart bridge support through the hub controller ? device functionality and configuration for usb host/slave swapping is also provided by external spi flash ? usb link power management (lpm) support ? suspend pin for remote wakeup indication to host ? start of frame (sof) synchronized clock output pin ? vendor specific messaging (vsm) support ? enhanced oem configuration options available through otp or smbus slave port ? flexible power rail support - vbus or vbat only operation - 3.3 v only operation - vbat + 1.8 v operation - 3.3 v + 1.8 v operation ? 48-pin (7x7 mm) qfn rohs compliant package target applications ? automotive head unit ? automotive breakout box ? navigation devices ? automotive consumer connectivity ports ? smart phones requiring host and device modes ? rear seat infotainment access key benefits ? multitrak tm - dedicated transaction translator per port ? portmap - configurable port mapping and disable sequencing ? portswap - configurable differential intra-pair signal swapping ? phyboost tm - programmable usb transceiver drive strength for recovering signal integrity ? varisense tm - programmable usb receiver sensitivity ? low power operation ? full power management with individual or ganged power control of each downstream port ? built-in self-powered or bus-powered internal default settings provide flexibility in the quantity of usb expansion ports utilized without redesign ? supports otp configurable flash ? fully integrated usb te rmination and pull-up/pull- down resistors ? on-chip power on reset (por) ? internal 3.3 v and 1.2 v voltage regulators ? on board 24 mhz crystal driver, resonator, or external 24 mhz clock input ? temperature range: -40 oc to 85 oc USB84604 usb 2.0 hsic hi-speed 4-port controller hub
USB84604 ds60001295c-page 2 ? 2014-2016 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2014-2016 microchip technology inc. ds60001295c-page 3 USB84604 table of contents 1.0 general description ....................................................................................................... ................................................................. 4 2.0 pin configuration ......................................................................................................... ................................................................... 7 3.0 pin descriptions .......................................................................................................... .................................................................... 8 4.0 power connections ......................................................................................................... .............................................................. 21 5.0 modes of operations ....................................................................................................... .............................................................. 23 6.0 device configuration ...................................................................................................... ............................................................... 27 7.0 device interfaces ......................................................................................................... ................................................................. 31 8.0 functional descriptions ................................................................................................... .............................................................. 37 9.0 operational charac teristics ............................................................................................... ............................................................ 40 10.0 package outline ........................................................................................................ ................................................................ 52 appendix a: data sheet revision history ....................................................................................... .................................................... 55 appendix b: terms and acronyms ................................................................................................ ..................................................... 56 appendix c: references ........................................................................................................ ............................................................. 57 the microchip web site ........................................................................................................ .............................................................. 58 customer change notification service .......................................................................................... ..................................................... 58 customer support .............................................................................................................. ................................................................. 58 product identification system ................................................................................................. ............................................................ 59
USB84604 ds60001295c-page 4 ? 2014-2016 microchip technology inc. 1.0 general description the microchip USB84604 is a low-power, oem configurable, mt t (multi-transaction translat or) usb 2.0 controller hub with 4 downstream ports and advanced features for embedded usb applications. the USB84604 is fully compliant with the usb 2.0 specification [ 2 ] , usb 2.0 link power management addendum, high-speed inter-chip (hsic) usb elec- trical specification revision 1.0 [ 4 ] , and will attach to an upstream port as a full-speed hub or as a full-/hi-speed hub. the 4-port hub supports low-speed, full-speed, and hi-s peed (if operating as a hi-speed hub) downstream devices on all of the enabled downstream (non-hsic) port s. hsic ports support only hi-speed operation. the USB84604 has been specifically optimized for em bedded systems where high performance and minimal bom costs are critical design requirements. standby mode pow er has been minimized and reference clock inputs can be aligned to the customer?s specific applic ation. flexible power rail options ease integration into energy efficient designs by allowing the USB84604 to be powered in a single-source (vbus, vbat, 3.3 v) or a dual-source (vbat + 1.8, 3.3 v + 1.8) configuration. a dditionally, all required resistors on the usb ports are integrated into the hub, including all series termination and pull-up/pull-down resistors on the d+ and d- pins. the USB84604 supports downstream battery charging. t he USB84604 includes embedded usb device/slave function- ality which is dedicated for use as a usb to i 2 c/spi interface, allowing external circ uits or devices to be monitored, con- trolled, or configured via the usb interface. addition ally, the USB84604 includes many powerful and unique features such as: flexconnect , which provides flexible connectivity options. th e USB84604?s downstream port 1 can be swapped with the upstream port, allowing master capable devices to control other devices on the hub. multitrak tm technology , which utilizes a dedicated transaction translato r (tt) per port to main tain consistent full- speed data throughput regardless of the number of active downstream connections. multitrak tm outperforms conven- tional usb 2.0 hubs with a single tt in usb full-speed data transfers. portmap , which provides flexible port mapping and disable s equences. the downstream ports of a USB84604 hub can be reordered or disabled in any sequenc e to support multiple platform designs with minimum effort. for any port that is disabled, the USB84604 hub controller automatically reorders the remaining port s to match the usb host controller?s port numbering scheme. portswap , which adds per-port programmability to usb differentia l-pair pin locations. portswap allows direct alignment of usb signals (d+/d-) to connectors to avoid uneven trace length or crossing of the usb differential signals on the pcb. phyboost , which provides programmable levels of hi-speed usb signal drive strength in the downstream port transce ivers. phyboost can restore usb signal integrity in a comp romised system environment. the graphic on the right shows an example of hi-speed usb eye diagrams befo re and after phyboost signal integrity restoration. varisense , which controls the usb receiver sensitivity enabling programmable lev- els of usb signal receive sensitivity. this capability allows operation in a sub-optimal system environment, such as when a captive usb cable is used. the USB84604 is available for the automotive temperature range (-40 oc to 85 oc). available firmware revisions are shown in the product identification system on page 59 : ?001080? and ?001070?. the ?001080? version enables the internal hub feature controller, while the ?001070? version disables it. there are no addi- tional differences between these two versions.
? 2014-2016 microchip technology inc. ds60001295c-page 5 USB84604 the hub feature controller adds advanced functionality to the USB84604 by enabling the host to send commands directly to it via the upstream usb c onnection. the hub feature controller in cludes a usb peripheral/slave controller that receives commands which are contained in the usb data packet. the following functions can be controlled via com- mands through the hub feature controller: ?i 2 c over usb bridging: the host can send commands thro ugh usb to any device connected to the hub through the smbus. ? uart over usb bridging: the host can send commands through usb to any device connected to the hub through the uart. for more details about uart functions refer to the sdk. ? spi over usb bridging: the host accesses to an attached spi device as a pass-through operation. ? gpio control: the gpios on the hub can be dynamically configured and controlled by the host. for more details about gpio functions refer to the sdk. ? otp programming: permanent customer configurations can be loaded to the one time programmable memory. ? flexconnect support: flexconnect allows the hub to dynamically change the physical ports that act as upstream and downstream ports. for more details refer to the flexconnect applications [ 9 ]. ? access to configuration registers
USB84604 ds60001295c-page 6 ? 2014-2016 microchip technology inc. 1.1 block diagram figure 1-1 details the internal block diagram of the USB84604. figure 1-1: system block diagram repeater hub controller sie serial interface to i2c master/slave routing & port re-ordering logic scl sda port controller vddcr12 tt #3 tt #2 tt #1 1.2 v reg reset_n vddcorereg tt #4 gpio port power tt #5 udc 20 2 kb dp sram 8051 controller spi spi/i2c gpio bridge 256 b iram vdda33 vbat 3.3 v reg swap phy usb down or upstream phy usb downstream phy usb downstream phy usb downstream flex phy up or downstream hsic/usb vdd33 4 kb sram 32 kb rom 2 kb otp flex hsic flex phy ocs
? 2014-2016 microchip technology inc. ds60001295c-page 7 USB84604 2.0 pin configuration the pin configuration depends on the firmware loaded (1070, 1080). the package designators are: ? USB84604 - product ? nnn - internal code - product revision yyww - year and work week ? tywwnna - lot # ? - country of origin ? ^^ - e3 pb free symbol figure 2-1: 48-qfn pin assignments (1070 , 1080) (top view) swap_usbdn1_dm/prt_dis_m1 swap_usbdn1_dp/prt_dis_p1 usbdn2_dm/prt_dis_m2 usbdn2_dp/prt_dis_p2 38 39 37 40 vdd12 41 flex_hsic_up_strobe 43 xtal2 44 xtal1/refclk rbias vdda33 vddcorereg flex_hsic_up_data 42 1 2 3 4 5 6 7 8 9 10 11 21 20 19 18 17 16 15 14 13 23 22 24 35 36 33 32 31 30 29 28 34 27 26 25 indicates pins on the bottom of the device. usbdn3_dm/prt_dis_m3 vddcr12 vddcr12 flex_usbup_dm/prt_dis_m0 flex_usbup_dp/prt_dis_p0 vdd33 reset_n pio10 scl/smbclk/pio2 sda/smbdata/pio45 uart_tx/ocs4_n/pio20 prtpwr4/pio44 vbus_det/pio16 uart_rx/ocs3_n/pio19 spi_clk/pio4 pio8 prtpwr3/pio43 ocs2_n/pio18 prtpwr2/pio42 ocs1_n/pio17 prtpwr1/pio41 spi_di/pio9 pio3 sof/pio1 vddcr12 vdd33 usbdn3_dp/prt_dis_p3 usbdn4_dm/prt_dis_m4 usbdn4_dp/prt_dis_p4 suspend/pio0 vbat vdda33 12 45 47 48 46 spi_do/spi_spd_sel/pio5 spi_ce_n vdda33 nc USB84604 nnnyyww tywwnnna ^^ ground pad (must be connected to vss)
USB84604 ds60001295c-page 8 ? 2014-2016 microchip technology inc. 3.0 pin descriptions this section provides a detailed description of each pin. the signals are arranged in functional groups according to their associated interface. the ?_n? symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. for example, reset _n indicates that the reset signal is acti ve low. when ?_n? is no t present after the signal name, the signal is asserted at the high voltage level. the terms assertion and negation are used exclusively. this is done to avoid confusion when working with a mixture of ?active low? and ?active high? signals. t he term assert, or assertion, indicate s that a signal is active, independent of whether that level is represented by a high or low voltage. t he term negate, or negation, indicates that a signal is inac- tive. note: the buffer type for each signal is indi cated in the buffer type column of table 3-1 . a description of the buffer types is provided in section 3.2 . note: compatibility with the microchip ucs8100x family of usb port power controllers requires the ucs8100x be connected on port 1 of the USB84604. additionally, both prtpwr1 and ocs1_n must be pulled high at power-on reset (por). table 3-1: pin descriptions num pins name symbol buffer type description usb/hsic interfaces 1 upstream usb d+ (flex port 0) flex_usbup_dp aio upstream usb port 0 d+ data signal. see note 1 . note: the upstream port 0 signals can be optionally swapped with the down- stream port 1 signals. port 0 d+ disable configuration strap prt_dis_p0 is this strap is used in conjunction with prt_dis_m0 to disable usb port 0. 0 = port 0 d+ enabled 1 = port 0 d+ disabled note: both prt_dis_p0 and prt_dis_m0 must be tied to vdd33 at reset to place port 0 into hsic mode. see note 2 for more information on configuration straps.
? 2014-2016 microchip technology inc. ds60001295c-page 9 USB84604 1 upstream usb d- (flex port 0) flex_usbup_dm aio upstream usb port 0 d- data signal. see note 1 . note: the upstream port 0 signals can be optionally swapped with the down- stream port 1 signals. port 0 d- disable configuration strap prt_dis_m0 is this strap is used in conjunction with prt_dis_p0 to disable usb port 0. 0 = port 0 d- enabled 1 = port 0 d- disabled note: both prt_dis_p0 and prt_dis_m0 must be tied to vdd33 at reset to place port 0 into hsic mode. see note 2 for more information on configuration straps. 1 upstream hsic data (flex port 0) flex_hsic_up_ data hsic upstream hsic port 0 data signal. see note 1 . note: the upstream port 0 signals can be optionally swapped with the down- stream port 1 signals. 1 upstream hsic strobe (flex port 0) flex_hsic_up_ strobe hsic upstream hsic port 0 strobe signal. see note 1 . note: the upstream port 0 signals can be optionally swapped with the down- stream port 1 signals. 1 downstream usb d+ (swap port 1) swap_usbdn1_ dp aio downstream usb port 1 d+ data signal. note: the downstream port 1 signals can be optionally swapped with the upstream port 0 signals. port 1 d+ disable configuration strap prt_dis_p1 is this strap is used in conjunction with prt_dis_m1 to disable usb port 1. 0 = port 1 d+ enabled 1 = port 1 d+ disabled note: both prt_dis_p1 and prt_dis_m1 must be tied to vdd33 at reset to dis- able the associated port. see note 2 for more information on configuration straps. table 3-1: pin descriptions (continued) num pins name symbol buffer type description
USB84604 ds60001295c-page 10 ? 2014-2016 microchip technology inc. 1 downstream usb d- (swap port 1) swap_usbdn1_ dm aio downstream usb port 1 d- data signal. note: the downstream port 1 signals can be optionally swapped with the upstream port 0 signals. port 1 d- disable configuration strap prt_dis_m1 is this strap is used in conjunction with prt_dis_p1 to disable usb port 1. 0 = port 1 d- enabled 1 = port 1 d- disabled note: both prt_dis_p1 and prt_dis_m1 must be tied to vdd33 at reset to dis- able the associated port. see note 2 for more information on configuration straps. 1 downstream usb d+ (port 2) usbdn2_dp aio downstream usb port 2 d+ data signal. port 2 d+ disable configuration strap prt_dis_p2 is this strap is used in conjunction with prt_dis_m2 to disable usb port 2. 0 = port 2 d+ enabled 1 = port 2 d+ disabled note: both prt_dis_p2 and prt_dis_m2 must be tied to vdd33 at reset to dis- able the associated port. see note 2 for more information on configuration straps. 1 downstream usb d- (port 2) usbdn2_dm aio downstream usb port 2 d- data signal. port 2 d- disable configuration strap prt_dis_m2 is this strap is used in conjunction with prt_dis_p2 to disable usb port 2. 0 = port 2 d- enabled 1 = port 2 d- disabled note: both prt_dis_p2 and prt_dis_m2 must be tied to vdd33 at reset to dis- able the associated port. see note 2 for more information on configuration straps. table 3-1: pin descriptions (continued) num pins name symbol buffer type description
? 2014-2016 microchip technology inc. ds60001295c-page 11 USB84604 1 downstream usb d+ (port 3) usbdn3_dp aio downstream usb port 3 d+ data signal. port 3 d+ disable configuration strap prt_dis_p3 is this strap is used in conjunction with prt_dis_m3 to disable usb port 3. 0 = port 3 d+ enabled 1 = port 3 d+ disabled note: both prt_dis_p3 and prt_dis_m3 must be tied to vdd33 at reset to dis- able the associated port. see note 2 for more information on configuration straps. 1 downstream usb d- (port 3) usbdn3_dm aio downstream usb port 3 d- data signal. port 3 d- disable configuration strap prt_dis_m3 is this strap is used in conjunction with prt_dis_p3 to disable usb port 3. 0 = port 3 d- enabled 1 = port 3 d- disabled note: both prt_dis_p3 and prt_dis_m3 must be tied to vdd33 at reset to dis- able the associated port. see note 2 for more information on configuration straps. 1 downstream usb d+ (port 4) usbdn4_dp aio downstream usb port 4 d+ data signal. port 4 d+ disable configuration strap prt_dis_p4 is this strap is used in conjunction with prt_dis_m4 to disable usb port 4. 0 = port 4 d+ enabled 1 = port 4 d+ disabled note: both prt_dis_p4 and prt_dis_m4 must be tied to vdd33 at reset to dis- able the associated port. see note 2 for more information on configuration straps. table 3-1: pin descriptions (continued) num pins name symbol buffer type description
USB84604 ds60001295c-page 12 ? 2014-2016 microchip technology inc. 1 downstream usb d- (port 4) usbdn4_dm aio downstream usb port 4 d- data signal. port 4 d- disable configuration strap prt_dis_m4 is this strap is used in conjunction with prt_dis_p4 to disable usb port 4. 0 = port 4 d- enabled 1 = port 4 d- disabled note: both prt_dis_p4 and prt_dis_m4 must be tied to vdd33 at reset to dis- able the associated port. see note 2 for more information on configuration straps. i 2 c/smbus interface 1i 2 c serial clock input scl i_smb i 2 c/smbus serial clock output (bridging) smbus clock smbclk i_smb i 2 c/smbus serial clock input general pur- pose i/o 2 pio2 is/o8/ od8 general purpose i/o 2 1i 2 c serial data sda is/od8 i 2 c bidirectional serial data smbus serial data smbdata is/od8 smbus bidirectional serial data general pur- pose i/o 45 pio45 is/o8 od8 general purpose i/o 45 spi master interface 1 spi chip enable output spi_ce_n o6 active-low spi chip enable output. note: if the spi is enabled, this pin will be driven high in powerdown states. 1 spi clock output spi_clk o6 spi clock output general pur- pose i/o 4 pio4 is/o6/ od6 general purpose i/o 4 note: if the spi is disabled, by setting the spi_master_dis bit in the util_- config1 register, this pin may be used as pio4. table 3-1: pin descriptions (continued) num pins name symbol buffer type description
? 2014-2016 microchip technology inc. ds60001295c-page 13 USB84604 1 spi data output spi_do o6 spi data output spi speed select configuration strap spi_spd_sel is (pd) this strap is used to select the speed of the spi. 0 = 30 mhz (default) 1 = 60 mhz note: if the latched value on reset is 1, this pin is tri-stated when the chip is in the suspend state. if the latched value on reset is 0, this pin is driven low during a suspend state. see note 2 for more information on configuration straps. general pur- pose i/o 5 pio5 is/o6/ od6 general purpose i/o 5 note: if the spi is disabled, by setting the spi_master_dis bit in the util_- config1 register, this pin may be used as pio5. 1 spi data input spi_di is (pd) spi data input general pur- pose i/o 9 pio9 is/o6/ od6 general purpose i/o 9 note: if the spi is disabled, by setting the spi_disable bit in the util_con- fig1 register, this pin may be used as pio9. misc. 1 port 1 over-current sense input ocs1_n is (pu) firmware 1070, 1080: this active-low signal is input from an external current monitor to indicate an over-current condition on usb port 1. general pur- pose i/o 17 pio17 is/o8/ od8 firmware 1070, 1080: general purpose i/o 17 1 port 2 over-current sense input ocs2_n is (pu) this active-low signal is input from an external current monitor to indicate an over-current condi- tion on usb port 2. general pur- pose i/o 18 pio18 is/o8/ od8 general purpose i/o 18 table 3-1: pin descriptions (continued) num pins name symbol buffer type description
USB84604 ds60001295c-page 14 ? 2014-2016 microchip technology inc. 1uart receive input uart_rx is internal uart receive input note: this is a 3.3 v signal. for rs232 oper- ation, an external 12 v translator is required. port 3 over-current sense input ocs3_n is (pu) this active-low signal is input from an external current monitor to indicate an over-current condi- tion on usb port 3. general pur- pose i/o 19 pio19 is/o8/ od8 general purpose i/o 19 1uart transmit out- put uart_tx o8 internal uart transmit output note: this is a 3.3 v signal. for rs232 oper- ation, an external 12 v driver is required. port 4 over-current sense input ocs4_n is (pu) this active-low signal is input from an external current monitor to indicate an over-current condi- tion on usb port 4. general pur- pose i/o 20 pio20 is/o8/ od8 general purpose i/o 20 1 system reset input reset_n i_rst this active-low signal allows external hardware to reset the device. note: the active-low pulse must be at least 5 s wide. refer to section 8.4.2, "external chip reset (reset_n)," on page 38 for additional information. 1 crystal input xtal1 iclk external 24 mhz crystal input reference clock input refclk iclk reference clock input. the device may be alter- natively driven by a single-ended clock oscillator. when this method is used, xtal2 should be left unconnected. crystal out- put xtal2 oclk external 24 mhz crystal output 1 external usb transceiver bias resistor rbias ai a 12.0 k ? (+/- 1%) resistor is attached from ground to this pin to set the transceiver?s internal bias settings. table 3-1: pin descriptions (continued) num pins name symbol buffer type description
? 2014-2016 microchip technology inc. ds60001295c-page 15 USB84604 1 suspend output suspend pu firmware 1070, 1080: this signal is used to indi- cate that the entire hub has entered the usb sus- pend state and that vbus current consumption should be reduced in accordance with the usb specification [ 2 ] . refer to section 8.6, "suspend (suspend)," on page 39 for additional informa- tion. note: suspend is disabled by default and must be enabled via the protouch configuration tool. general pur- pose i/o 0 pio0 is/o8/ od8 firmware 1070, 1080: general purpose i/o 0 note: if the suspend output is disabled, this pin may be used as pio0. 1 sof syn- chronized 8 khz clock output sof o8 this signal outputs an 8 khz clock synchronized with the usb host sof. note: sof output is controlled via the sof_enable bit in the util_con- fig1 register. this feature is not enabled by default. general pur- pose i/o 1 pio1 is/o8/ od8 general purpose i/o 1 note: if the sof output is disabled, by clear- ing the sof_enable bit in the util_- config1 register, this pin may be used as pio1. 1 detect upstream vbus power vbus_det is detects state of upstream bus power. when designing a detachable hub, this pin must be connected to the vbus power pin of the upstream usb port through a resistor divider (50 k ? by 100 k ? ) to provide 3.3 v. for self-powered applications with a permanently attached host, this pin must be connected to either 3.3 v or 5.0 v through a resistor divider to provide 3.3 v. in embedded applications, vbus_det may be controlled (toggled) when the host desires to renegotiate a connection without requiring a full reset of the device. general pur- pose i/o 16 pio16 is/o8/ od8 general purpose i/o 16 table 3-1: pin descriptions (continued) num pins name symbol buffer type description
USB84604 ds60001295c-page 16 ? 2014-2016 microchip technology inc. 1 port 1 power output prtpwr1 o8 firmware 1070, 1080: enables power to a down- stream usb device attached to port 1. 0 = power disabled on downstream port 1 1 = power enabled on downstream port 1 general pur- pose i/o 41 pio41 is/o8/ od8 general purpose i/o 41 1 port 2 power output prtpwr2 o8 enables power to a downstream usb device attached to port 2. 0 = power disabled on downstream port 2 1 = power enabled on downstream port 2 general pur- pose i/o 42 pio42 is/o8/ od8 general purpose i/o 42 1 port 3 power output prtpwr3 o8 enables power to a downstream usb device attached to port 3. 0 = power disabled on downstream port 3 1 = power enabled on downstream port 3 general pur- pose i/o 43 pio43 is/o8/ od8 general purpose i/o 43 1 port 4 power output prtpwr4 o8 enables power to a downstream usb device attached to port 4. 0 = power disabled on downstream port 4 1 = power enabled on downstream port 4 general pur- pose i/o 44 pio44 is/o8/ od8 general purpose i/o 44 1 general pur- pose i/o 3 pio3 is/o8/ od8 general purpose i/o 3 1 general pur- pose i/o 8 pio8 is/o8/ od8 general purpose i/o 8 1 general pur- pose i/o 10 pio10 is/o8/ od8 general purpose i/o 10 1 no connect nc - these pins must be left floating for normal device operation. power table 3-1: pin descriptions (continued) num pins name symbol buffer type description
? 2014-2016 microchip technology inc. ds60001295c-page 17 USB84604 note 1: when the device is configured to enable the hsic up stream port, the usb product id (pid) will be 0x4604. when the device is configured to enable the u sb upstream port, the usb pid will be 0x4504. 1 battery power supply input vbat p battery power supply input. when vbat is con- nected directly to a +3.3 v supply from the sys- tem, the internal +3.3 v regulator runs in dropout and regulator power consumption is eliminated. a 4.7 f (<1 ? esr) capacitor to ground is required for regulator stability. the capacitor should be placed as close as possible to the device. refer to chapter 4.0 power connections on page 21 for power connection information. 3+3.3v analog power supply vdda33 p +3.3 v analog power supply. a 1.0 f (<1 ? esr) capacitor to ground is required for regulator stabil- ity. the capacitor should be placed as close as possible to the device. refer to chapter 4.0 power connections on page 21 for power connec- tion information. 2+3.3v power supply vdd33 p +3.3 v power supply. these pins must be con- nected to vdda33. refer to chapter 4.0 power connections on page 21 for power connection information. 1 +1.8 - 3.3 v core power supply input vddcorereg p +1.8 - 3.3 v core pow er supply inpu t to internal +1.2 v regulator. this pin may be connected to vdd33 for single supply applications when vbat equals +3.3 v. running in a dual supply configu- ration with vddcorereg at a lower voltage, such as +1.8 v, may redu ce overall system power consumption. in dual supply configurations, a 4.7 f (<1 ? esr) capacitor to ground is required for regulator stability. the capacitor should be placed as close as possible to the device. refer to chapter 4.0 power connections on page 21 for power connection information. 3 +1.2v core power supply vddcr12 p +1.2 v core power supply. in single supply appli- cations or dual supply applications where 1.2 v is not used, a 1.0 f (<1 ? esr) capacitor to ground is required for regulator stability. the capacitor should be placed as close as possible to the device. refer to chapter 4.0 power connec- tions on page 21 for power connection informa- tion. 1 +1.2 v hsic power supply input vdd12 p +1.2 v hsic power supply input. refer to chapter 4.0 power connections on page 21 for power connection information. exposed pad on package bot- tom ( figure 2-1 ) ground vss p common ground. this exposed pad must be con- nected to the ground plane with a via array. table 3-1: pin descriptions (continued) num pins name symbol buffer type description
USB84604 ds60001295c-page 18 ? 2014-2016 microchip technology inc. note 2: configuration strap values are latc hed on power-on reset (por) and the rising edge of reset_n (exter- nal chip reset). configuration stra ps are identified by an underlined symbol name. signals that function as configuration straps must be augm ented with an external resistor wh en connected to a load. refer to sec- tion 6.3, "device configuration straps," on page 29 for additional information.
? 2014-2016 microchip technology inc. ds60001295c-page 19 USB84604 3.1 pin assignments if the pin assignment is different fo r the firmware revisions (1070, 1080), it is mentioned within the table. table 3-2: 48-qfn package pin assignments pin num pin name pin num pin name 1 vbat 25 spi_ce_n 2 vddcr12 26 spi_do/spi_spd_sel /pio5 3 usbdn1_dm/prt_dis_m1 27 spi_clk/pio4 4 usbdn1_dp/prt_dis_p1 28 uart_rx/ocs3_n/pio19 5 usbdn2_dm/prt_dis_m2 29 prtpwr4/pio44 6 usbdn2_dp/prt_dis_p2 30 uart_tx/ocs4_n/pio20 7 vddcr12 31 sda/smbdata/pio45 8 usbdn3_dm/prt_dis_m3 32 vdd33 9 usbdn3_dp/prt_dis_p3 33 scl/smbclk/pio2 10 usbdn4_dm/prt_dis_m4 34 1070, 1080: pio10 11 usbdn4_dp/prt_dis_p4 35 reset_n 12 vdda33 36 vbus_det/pio16 13 sof/pio1 37 vdda33 14 1070, 1080: suspend/pio0 38 vdd12 15 1070, 1080: prtpwr1/pio41 39 flex_hsic_up_strobe 16 1070, 1080: ocs1_n/pio17 40 flex_usbup_dm/prt_dis_m0 17 vddcr12 41 flex_usbup_dp/prt_dis_p0 18 vdd33 42 flex_hsic_up_data 19 prtpwr2/pio42 43 xtal2 20 ocs2_n/pio18 44 xtal1/refclk 21 prtpwr3/pio43 45 nc 22 1070, 1080: pio3 46 rbias 23 1070, 1080: pio8 47 vddcorereg 24 spi_di/pio9 48 vdda33
USB84604 ds60001295c-page 20 ? 2014-2016 microchip technology inc. 3.2 buffer type descriptions table 3-3: buffer types buffer type description is schmitt-triggered input i_rst reset input i_smb i2c/smbus clock input o6 output with 6 ma sink and 6 ma source od6 open-drain output with 6 ma sink o8 output with 8 ma sink and 8 ma source od8 open-drain output with 8 ma sink hsic high-speed inter-chip (hsic) usb specification, version 1.0 [ 4 ] compliant input/output pu 50 a (typical) internal pull-up. unless other wise noted in the pin description, internal pull- ups are always enabled. note: internal pull-up resistors prevent unconnect ed inputs from floating. do not rely on internal resistors to drive signals exte rnal to the device. when connected to a load that must be pulled high, an ex ternal resistor must be added. pd 50 a (typical) internal pull-down. unless ot herwise noted in the pin description, internal pull-downs are always enabled. note: internal pull-down resistors prevent unconn ected inputs from floating. do not rely on internal resistors to drive signals exte rnal to the device. when connected to a load that must be pulled low, an external resistor must be added. aio analog bi-directional iclk crystal oscillator input pin oclk crystal oscillator output pin p power pin
? 2014-2016 microchip technology inc. ds60001295c-page 21 USB84604 4.0 power connections 4.1 integrated power regulators the integrated 3.3 v a nd 1.2 v power regulators provide flexibility to th e system in providing power the device. several different configurations are allowed in order to align the power structure to s upplies available in the system. the regulators are controlled by reset _n. when reset_n is brought high, t he 3.3 v regulator will turn on. when reset_n is brought low the 3.3 v regulator will turn off. 4.1.1 3.3 v regulator the device has an integrated regulato r to convert from vbat to 3.3 v. 4.1.2 1.2 v regulator the device has an integrated regulator to convert from a variable voltage input on vddcorereg to 1.2 v. the 1.2 v regulator is tolerant to the presence of low voltage (~0 v) on the vddcorereg pin in order to support system power solutions where a supply is not always present in low power states. the 1.2 v regulator supports an input volt age range consistent with a 1.8 v input in order to reduce power consumption in systems which provide multiple power supply levels. in addition, the 1.2 v regulator supports an input voltage up to 3.3 v for systems which provide only a si ngle power supply. the device will supp ort operation where th e 3.3 v regulator output can drive the 1.2 v regul ator input such that vbat is the only required supply. 4.2 power configurations the device supports operation with no ba ck current when power is connected in each of the following configurations. power connection diagrams for these configurations are included in section 4.3, "power connection diagrams," on page 22 . 4.2.1 single suppl y configurations 4.2.1.1 vbat only vbat may be tied to the vbat system supply. vdd33, v dda33, and vddcorereg must be tied together on the board. in this configuration the 3.3 v and 1.2 v regulators will be active. for hsic operation, vdd12 may be tied to vddcr12. 4.2.1.2 3.3 v only vbat may be tied to the 3.3 v system supply. vdd33, v dda33, and vddcorereg must be tied together on the board. in this configuration the 3.3 v regulator will operate in dropout mode and the 1.2 v regulator will be active. for hsic operation, vdd12 may be tied to vddcr12. 4.2.2 dual supply configurations 4.2.2.1 vbat + 1.8 v vbat may be tied to the vbat system supply. vddcorereg ma y be tied to the 1.8 v system supply. in this configu- ration, the 3.3 v regulator and the 1.2 v regulator will be ac tive. for hsic operation, vdd12 may be tied to vddcr12. 4.2.2.2 3.3 v + 1.8 v vbat may be tied to the 3.3 v system supply. vddcorereg ma y be tied to the 1.8 v system supply. in this configu- ration the 3.3 v regulator will operate in dropout mode and the 1.2 v regulator will be active. for hsic operation, vdd12 may be tied to vddcr12.
USB84604 ds60001295c-page 22 ? 2014-2016 microchip technology inc. 4.3 power connection diagrams figure 4-1 illustrates the power connections for the usb8 4604 with various power supply configurations. figure 4-1: power connections note: to achieve the lowest power possible, tie the vdd12 pin to vddcr12. hsic 3.3 v regulator (in) (out) vbat vbat supply 1.2 v core logic 3.3 v i/o USB84604 single supply application 1.2 v regulator (in) (out) 3.3 v internal logic vdda33 (3x) 1.0 f vddcorereg vddcr12 1.0 f vss hsic 3.3 v regulator (in) (out) vbat vbat supply 1.2 v core logic 3.3 v i/o USB84604 dual supply application 1.2 v regulator (in) (out) 3.3 v internal logic 1.0 f vddcorereg vddcr12 1.0 f +1.8 v supply vdd33 (2x) hsic only vdda33 (3x) vdd33 (2x) vdd12 vdd12 4.7 f vss 4.7 f 4.7 f hsic only
? 2014-2016 microchip technology inc. ds60001295c-page 23 USB84604 5.0 modes of operations the device provides two main modes of operation: standb y mode and hub mode. the operating mode of the device is selected by setting values on primary inputs according to the table below. the flowchart in figure 5-1 shows the modes of operation. it also show s how the device traverses through the hub mode stages (shown in bold). the flow of c ontrol is dictated by control register bits shown in italics as well as other events such as availability of a reference clock. the remain ing sections in this chapter provide more detail on each stage and mode of operation. table 5-1: controlling modes of operation reset_n input resulting mode summary 0 standby lowest power mode : no functions are active other than monitoring the reset_n input. all port interfaces are high impedance. all regulators are pow- ered off. 1 hub full feature mode : device operates as a configurable usb hub. power con- sumption is based on the number of acti ve ports, their speed, and amount of data transferred. note: refer to section 8.4.2, "ext ernal chip reset (reset_n)," on page 38 for additional information on reset_n.
USB84604 ds60001295c-page 24 ? 2014-2016 microchip technology inc. figure 5-1: hub operat ional mode flowchart yes no combine otp config data soc done? config load from internal rom external spi rom present? yes no run from internal rom run from external spi rom do smbus or i2c initialization sw upstream bc detection (chgdet) hub connect (hub.connect) (hub_cfg) no (soc_cfg) (sw_init) normal operation smbus or i2c present? yes (hw_init)
? 2014-2016 microchip technology inc. ds60001295c-page 25 USB84604 5.1 boot sequence 5.1.1 standby mode if the external hardware reset is assert ed, the hub will be in standby mode. this mode provides a very low power state for maximum power efficiency when no signaling is required. this is the lowest power state. in standby mode all internal regulators are powered off, the pll is not running, and core logic is powered down in order to minimize power consump- tion. because core logic is powered off, no configuration settings are retained in this mode and must be re-initialized after reset_n is negated high. 5.1.2 hardware initialization stage (hw_init) the first stage is the initialization stage and occurs on t he negation of reset_n. in this stage the 1.2 v regulator is enabled and stabilizes, in ternal logic is reset, and the pl l locks if a valid refclk is su pplied. configur ation registers are initialized to their default state and strap input values are latched. the device will complete initialization and auto- matically enter the next stage. because the digital logic withi n the device is not yet stable, no communication with the device using the smbus is possible. configuration registers are initialized to their default state. if there is a refclk presen t, the next state is sw_init. 5.1.3 software initialization stage (sw_init) once the hardware is in itialized, the firmware c an begin to execute. th e internal firmware checks for an external spi rom. the firmware looks for an external spi flash device that contains a valid signature of ?2dfu? (device firmware upgrade) beginning at address 0xfffa. if a valid signature is found, then the external rom is enabled and the code execution begins at address 0x00 00 in the external spi device. if a valid signa ture is not found, th en execution continues from internal rom. spi roms used with the device must be 1 mbit and suppor t either 30 mhz or 60 mhz. the frequency used is set using the spi_spd_sel configuration strap. both 1- and 2-bi t spi operation is supported. for optimum throughput, a 2-bit spi rom is recommended. both mode 0 and mode 3 spi roms are also supported. refer to sec- tion 6.3.2, "spi speed select (spi_spd_sel)," on page 30 for additional information on selection of the spi speed. for all other configurations, the firmware checks for the presence of an external i 2 c/smbus. it does this by asserting two pull down resistors on the data and clo ck lines of the bus. the pull downs are 50 k ? . if there are 10 k ? pull-ups present, the device becomes aware of the presence of an external smbus/i 2 c bus. if a bus is detected, the firmware transitions to the soc_cfg state. 5.1.4 soc configuration stage (soc_cfg) in this stage, the soc may modify any of the default configur ation settings specified in t he integrated rom such as usb device descriptors, or port electrical settings. there is no time limit. in this stage the firmware will wait indefinitely for the smbus/i 2 c configuration. when the soc has completed configuring the device, the attach command (a a55h) must be sent. refer to the application note smbus slave interface for the usb253x/usb3x13/usb46x4 [ 7 ] . 5.1.5 hub configurati on stage (hub_cfg) once the soc has indicated that it is done with configurat ion, then all the configuration data is combined. the default data, the soc configuration data, the ot p data are all combined in the firmware and the device is programmed. if the soc_cfg state is evaluated, and the otp data will be added to the soc settings. after the device is fully configured, it will go idle and then into suspend if there is no vb us or hub.connect present. if vbus is present, and upstream battery charging is not enabl ed, the device will transition to the connect (hub.connect) stage. 5.1.6 hub connect stage (hub.connect) once the chgdet stage is completed, the device enters th e hub.connect stage. the hub connect stage is when the hub will begin operation according to the usb 2.0 specification [ 2 ] . the hub will monitor the vbus_det pin, and when the signal is high, it will enable the 1.5 k ? pu on dp and enumerate with the host. note: otp can overwrite any configurat ion the soc did as shown in figure 5-1 .
USB84604 ds60001295c-page 26 ? 2014-2016 microchip technology inc. 5.1.7 normal mode lastly the soc enters the normal mode of operation. in this stage, full usb operation is su pported under control of the usb host on the upstream port. the device will remain in the normal mode until the op erating mode is changed by the system. the only device registers accessible to the soc are the run time registers described in an 26.18 smbus slave interface for the usb253x/usb3x13/usb46x4 [ 7 ]. if reset_n is asserted low, then stan dby mode is entered . the device may then be plac ed into any of the designated hub stages. asserting the soft disconnect on the upstream po rt will cause the hub to return to the hub.connect stage until the soft disc onnect is negated. to save power, communication over the smbus is not su pported while in usb suspend. the system can prevent the device from going to sleep by asserting the clksusp contro l bit of the configure portable hub register (described in an 26.18 smbus slave interface fo r the usb253x/usb3x13/usb46x4 [ 7 ]) anytime before entering usb suspend. while the device is kept awake during usb su spend, it will provide the smbus functi onality at the expense of not meeting usb requirements for average suspend current consumption.
? 2014-2016 microchip technology inc. ds60001295c-page 27 USB84604 6.0 device configuration the device supports a large number of features (some mutually ex clusive), and must be configured in order to correctly function when attached to a usb host controller. the hub can be configured either internal ly or externally depending on the implemented interface. microchip provides a comprehensive software programming tool, protouch, fo r configuring the USB84604 functions, registers and otp memory. all configuration is to be perfor med via the protouch programming tool. for additional infor- mation on the protouch programming tool, contac t your local microchip sales representative. 6.1 configuration method selection the hub will interface to external memory depending on the configuration of the device pins associated with each inter- face type. the device will first check whet her an external spi rom is present. if present, the device will operate entirely from the external rom. when an external spi rom is not pr esent, the device will check wh ether the smbus is config- ured. when the smbus is enabled, it can be used to configure the internal device registers vi a the configuration registers address space, or to program the internal otp memory. if no external options are detected, the device will operate using the internal default and configuration st rap settings. the order in which device configuration is attempted is summarized below: 1. spi (reading the configuration from an spi rom) 2. smbus (either writing the configuration registers in the xdata address space, or to otp) 3. internal default settings (with or without configuration strap over-rides) 6.2 customer accessible functions the following usb or smbus accessible functions are avail able to the customer via the microchip protouch program- ming tool. 6.2.1 usb accessible functions 6.2.1.1 i 2 c master access over usb access to i 2 c devices is performed as a pass-through operation from the usb host. the device firmware has no knowl- edge of the operation of the attached i 2 c device. the supported commands can be found on our web site at www.microchip.com . refer to the product page of the USB84604. note: refer to chapter 7.0 device interfaces on page 31 for detailed information on each device configuration interface. note: for additional programming details, refer to the microchip protouch programming tool user manual.
USB84604 ds60001295c-page 28 ? 2014-2016 microchip technology inc. 6.2.1.2 spi access over usb access to an attached spi device is performed as a pass-thr ough operation from the usb host. the device firmware has no knowledge of the operation of the attached spi device. the supported commands can be found on our web site at www.microchip.com . refer to the product page of the USB84604. 6.2.1.3 otp access over usb the otp rom in the device is accessible via the usb bus. a ll otp parameters can be modified via the usb host. the otp operates in single-ended mode. the support ed commands can be found on our web site at www.microchip.com . refer to the product page of the USB84604. note: refer to section 7.1, "spi interface," on page 31 for additional information on the spi interface.
? 2014-2016 microchip technology inc. ds60001295c-page 29 USB84604 6.2.2 smbus acc essible functions 6.2.2.1 otp access over smbus the device?s otp rom is accessible over smbus. all otp parameters can be modified via the smbus host. the otp can be programmed to operate in single-ended, differentia l, redundant, or differential redundant mode, depending on the level of reliability required. the supported commands can be found on our web site at www.microchip.com . refer to the product page of the USB84604. 6.2.2.2 configuration access over smbus the functions that are available over smbus prior to the hub attaching to the usb host are described in an 26.18 smbus slave interface for the usb253x/usb3x13/usb46x4 [ 7 ]. 6.2.2.3 run time access over smbus there is a limited number of registers that are accessible via the smbus du ring run time operation of the device. refer to an 26.18 smbus slave interface for the usb253x/usb3x13/usb46x4 [ 7 ] for details. 6.3 device configuration straps configuration straps are multi-function pins that ar e driven as outputs during normal operation. during a power-on reset (por) or an external chip reset (reset_n) , these outputs are tri-stated. the hi gh or low state of the signal is latched following de-assertion of the reset and is used to dete rmine the default configuration of a particular feature. con- figuration straps are latc hed as a result of a power-on reset (por) or a external chip reset (reset_n) . configuration strap signals are noted in chapter 3.0 pin descriptions on page 8 and are identified by an underlined symbol name. the following sub-sections detail the various configuration straps. configuration straps include internal resistors in order to pr event the signal from floating w hen unconnected. if a partic- ular configuration strap is connected to a load, an external pull-up or pull-down should be used to augment the internal resistor to ensure that it reaches the required voltage level prior to latching. the internal resistor can also be overridden by the addition of an external resistor. 6.3.1 port disable (prt_dis_m x /prt_dis_p x ) these configuration straps disable the associated usb ports d- and d+ signals, respectively, where ? x ? is the usb port number. both the negative ?m? and positive ?p? port disable configuration straps for a given usb port must be tied high at reset to disable the associated port. note: the system designer must guarantee that configuration stra ps meet the timing requirements specified in section 9.6.2, "reset and confi guration strap timing," on page 48 and section 9.6.1, "power-on config- uration strap valid timing," on page 47 . if configuration straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values. note: configuration straps must never be driven as inputs . if required, configuration straps can be augmented, or overridden with external resistors. table 6-1: prt_dis_m x /prt_dis_p x configuration definitions prt_dis_m x /prt_dis_p x definition ?0? port x d-/d+ signal is enabled (default) ?1? port x d-/d+ signal is disabled
USB84604 ds60001295c-page 30 ? 2014-2016 microchip technology inc. 6.3.2 spi speed select (spi_spd_sel ) this strap is used to select the speed of the spi as follows: 6.4 spi external flash all spi eeprom programming is performed via the upstr eam usb connection of the hub. the hub must be powered on and enumerated (connected) to the usb host pc. two types of files may be programmed to the spi eeprom: ? complete firmware file obtained from microchip. ? user generated configuration f ile created with protouch2. the external flash can be programmed using the microchip protouch2 mpt software tool which can be downloaded from the microchip website at ht tp://www.microchip.com/protouch. 6.4.1 compatible devices the spi eeprom must conform to the following requirem ents in order to be compatible with microchip hubs: ? 60 mhz clock rate ? dual data read capable ? 2 mb or larger capacity (recommended) 6.4.2 obtaining firmware images firmware images alter the base functionality of the uch hu b. firmware images must be provided by microchip, they are not user-generated. to obtain the latest firmware rele ases, consult the product pages (documentation and software section) of the devices above. 6.4.3 obtaining configuration files configuration files are user-generated f iles that change basic operational parame ters of the hub such as changing ven- dor ids, disabling downstream ports, or adjusting the phyboost or varisense settings. configuration files can be gen- erated using the original prot ouch graphical user interface. table 6-2: spi_spd_sel configuration definitions spi_spd_sel definition ?0? 30 mhz spi operation (default) ?1? 60 mhz spi operation note: if the latched value on reset is 1, this pin is tri-stated when the chip is in the suspend state. if the latched value on reset is 0, this pin is driven low during a suspend state. note: refer to the protouch mpt user manual on using this software to program the configuration. it can be downloaded from the same website.
? 2014-2016 microchip technology inc. ds60001295c-page 31 USB84604 7.0 device interfaces the USB84604 provides multiple interfac es for configuration and external memory access. this chapter details the var- ious device interfaces and their usage. 7.1 spi interface the device is capable of code executio n from an external spi rom. on power up, the firmware looks for an external spi flash device that contains a valid signature of 2dfu (device firmware upgrade) beginning at address 0xfffa. if a valid signature is found, then the ex ternal rom is enabled and the code exec ution begins at address 0x0000 in the external spi device. if a valid signature is not found, then execution continues from inter nal rom. the following sections describe the interface options to the external spi rom. the spi interface is always enabled af ter reset. it can be dis abled by setting the spi_di sable bit in the util_con- fig1 register. 7.1.1 operation of the hi-speed read sequence the spi controller will automatically handle code reads going out to the spi rom address. when the controller detects a read, the controller drives spi_ce_n low, and outputs 0x 0b, followed by the 24-bit addres s. the spi controller outputs a dummy byte. the next eight clocks will cloc k in the first byte. when the first byte is clocked-in, a ready signal is sent back to the processor, and the processor gets one byte. after the processor gets the first byte, its address will change. if the address is one more t han the last address, the spi controller will clock out one more byte. if the address is any thing other than one more than the last address, the spi controller will terminate the transactio n by driving spi_ce_n high. as long as the addresses are sequential, the spi controller will continue clocking data in. 7.1.2 operation of the dual high speed read sequence the spi controller also supports dual data mode. when co nfigured in dual mode, the spi controller will automatically handle xdata reads going out to the spi rom. when the cont roller detects a read, the controller drives spi_ce_n low and outputs 0x3b (the value must be programmed into th e spi_ fr_opcode register) followed by the 24-bit address. bits 23 through bit 17 are forced to zero, and address bits 16 through 0 are directly from the xdata address bus. because it is in fast read mode, the spi controller then outputs a dummy byte. the next four clocks will clock in the first byte. the data appears two bits at a time on spi_do a nd spi_di. when the first byte is clocked in, a ready signal is sent back to the processor, and the processor gets one byte. note: for information on device configuration, refer to chapter 6.0 device configuration on page 27 . note: for spi timing information, refer to section 9.6.7, "spi timing," on page 49 . figure 7-1: spi hi-speed read sequence spi_ce_n spi_clk spi_do spi_di 8 0b msb high impedance 15 16 123 4 05 7 6 d out add. 23 24 add. add. x 39 40 31 32 47 48 55 56 63 64 71 72 80 d out nn+1 d out n+2 d out n+3 d out n+4 msb msb
USB84604 ds60001295c-page 32 ? 2014-2016 microchip technology inc. after the processor gets the first byte, its address will change. if the address is one more than the last address, the spi controller will clock out one more byte. if the address is any thing other than one more than the last address, the spi controller will terminate the transactio n by driving spi_ce_n high. as long as the addresses are sequential, the spi controller will continue clocking data in. 7.1.3 32 byte cache there is a 32-byte pipeline cache with an associated base addr ess pointer and length pointer. once the spi controller detects a jump, the base address pointer is initialized to that address. as each new sequential data byte is fetched, the data is written into the cache and the length is increment ed. if the sequential run exceeds 32 bytes, the base address pointer is incremented to indicate the last 32 bytes fetched. if the firmware performs a jump, and the jump is in the cache address range, the fetch is done in 1 clock from the internal cache instead of an external access. 7.1.4 interface oper ation to the spi port when not performing fast reads there is a 8-byte command buffer (spi_cmd_buf[7:0]) , an 8-byte response buffer (spi_resp_buf[7:0]), and a length register that counts out the numbe r of bytes (spi_cmd_len). additionally, there is a self-clearing go bit in the spi_ctl register. once the go bit is set, device drives spi_ce_n low and star ts clocking. it will then output spi_cm- d_len x 8 number of clocks. after the first command byte has been sent out, the spi_di input is stored in the spi_resp buffer. if the spi_cmd_len is longer than the spi_cmd_buf, don?t cares are sent out on the spi_do out- put. this mode is used for program execution out of internal ram or rom. automatic reads and writes happen when there is an external xdata read or write, using the serial stream that has been previously discussed. figure 7-2: spi dual hi -speed read sequence spi_ce_n spi_clk spi_do spi_di 8 3b msb high impedance 15 16 123 4 05 7 6 d1 add. 23 24 add. add. x 39 40 31 32 44 47 48 51 52 55 56 59 d2 nn+1 d3 n+2 d4 n+3 d5 n+4 msb msb d1 d2 n n+1 d3 n+2 d4 n+3 d5 n+4 msb 43 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-7,5,3,1 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-6,4,2,0 bits-7,5,3,1 bits-6,4,2,0
? 2014-2016 microchip technology inc. ds60001295c-page 33 USB84604 7.1.5 erase example to perform a sctr_erase, 32blk_erase, or 64blk_erase, the device writes 0x20, 0x 52, or 0xd8, respectively to the first byte of the command buffer, followed by a 3-byte address. the length of the transfer is set to 4 bytes. to perform this, the device drives spi_ce_n low, then counts out 8 clocks. it then outputs on spi_do the 8 bits of com- mand, followed by 24 bits of address of the location to be erased. when the transfer is complete, spi_ce_n goes high, while the spi_di line is ignored in this example. 7.1.6 byte program example to perform a byte program, the device writes 0x02 to the firs t byte of the command buffer, followed by a 3-byte address of the location that will be written to, and one data byte. the l ength of the transfer is set to 5 bytes. the device first driv es spi_ce_n low, then spi_do outputs 8 bits of command, followed by 24 bits of address, and one byte of data. spi_di is not used in this example. 7.1.7 command only program example to perform a single byte command such as the following: ?wrdi ?wren ?ewsr ? chip_erase ? ebsy ? dbsy the device writes the opcode into the first byte of the spi_cmd_buf and the spi_cmd_len is set to one. the device first drives spi_ce_n low, then 8 bits of the command are cl ocked out on spi_do. spi_di is not used in this example. figure 7-3: spi erase sequence spi_ce_n spi_clk 16 23 24 31 15 123 4 05 7 6 add. spi_do spi_di 8 command msb msb add. add. high impedance
USB84604 ds60001295c-page 34 ? 2014-2016 microchip technology inc. 7.1.8 jedec-id read example to perform a jedec-id command, the device writes 0x9f into the first byte of the spi_cmd_buf. the length of the transfer is 4 bytes. the device first drives spi_ce_n low, then spi_do is output with 8 bi ts of the command, followed by the 24 bits of dummy bytes (due to the length being set to 4). when the transfer is complete, spi_ce_n goes high. after the first byte, the data on spi_d i is clocked into the spi_rsp_buf. at the end of the command, there are three valid bytes in the spi_rsp_buf. in this example, 0xbf, 0x25, 0x8e. figure 7-4: spi command only sequence spi_ce_n spi_clk 1234 057 6 spi_do spi_di command msb high impedance
? 2014-2016 microchip technology inc. ds60001295c-page 35 USB84604 7.2 i 2 c master interface the i 2 c master interface implements a subset of the i 2 c master specification (please refer to the philips semiconductor standard i 2 c-bus specification for details on i 2 c bus protocols) [ 5 ] . the device?s i 2 c master interface relates to the standard-mode i 2 c specification (i.e., roundabout 67 kbit/s transfer ra te and 7-bit addressing) for protocol and electrical properties. the device acts as the ma ster and generates the serial clock sc l, controls the bus access (determines which device acts as the transmitter and which device acts as the receiver), and gener ates the start and stop con- ditions. 7.2.1 pull-up resistors for i 2 c the circuit board designer is required to place external pull-up resistors (10 k ? recommended) on the sda & scl sig- nals (per smbus 1.0 specification) [ 6 ] to vcc in order to assure proper operation. figure 7-5: spi jedec-id read sequence note: extensions to the i 2 c specification are not supported. note: all device configuration must be pe rformed via the microchip protouch programming tool. for additional information on the protouch programming tool, contact your local microchip sales representative. for the latest version of the tool refer to the pro duct page of the USB84604 on our web site at www.micro- chip.com . spi_ce_n spi_clk spi_do spi_di 8 9f msb high impedance 11 12 13 14 15 16 123 4 05 7 6 10 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 bf 25 8e msb msb
USB84604 ds60001295c-page 36 ? 2014-2016 microchip technology inc. 7.3 smbus slave interface the USB84604 includes an integrated smbus slave interface, which can be used to access internal device run time registers or program the internal otp memory. smbus dete ction is accomplished by detection of pull-up resistors (10 k ? recommended) on both the smbdata and smbclk signal s. to disable the smbus, a pull-down resistor of 10 k ? must be applied to smbdata. the smbus interface can be used to configure the device as detailed in section 6.1, "configuration method selection," on page 27 . the application note an 26.18 smbus slave interface for the usb253x/usb3x13/usb46x4 [ 7 ] provides additional information about register definitions. refer to t he product page of the USB84604 on our web site at www.micro- chip.com . note: all device configuration must be performed via the microchip protouch programming tool. for additional information on the protouch programming tool, contact your local microchip sales representative.
? 2014-2016 microchip technology inc. ds60001295c-page 37 USB84604 8.0 functional descriptions this chapter provides additional functional descriptions of key device features. alte rnatively links to references are pro- vided. 8.1 battery charger charging the USB84604 supports downstream batte ry charging. the application note an 26.19 usb battery charging with the microchip/smsc usb2534 hub controller [ 8 ] provides additional information about battery charging. 8.2 sof clock output the USB84604 provides an 8 khz clock output synchronized to the usb host sofs. the sof output is generated from the previous sof packet on the usb line. the device includes an internal free running frame counter to generate inter- nal start of frame and end of frame events. the internal co unter is re-synchronized ever y time a successful packet is received and decoded. the internal counter is advanced to compensate for the packet decode time. if the incoming sof jitters early or late, the jitter will be visible in the next frame sof output clock rising edge. if one or two sofs are missing, the so f output will continue based on the intern al frame counter. if more than two sof are missing, the sof output signal will stop. the clock is guar anteed to stop in a low state. when enabled or disabled, there will never be a short cycle. 8.3 flex connect this feature allows the upstream port to be swapped with do wnstream physical port 1. only downstream port 1 can be swapped physically. using port remapping, any logical port (number assignment) can be swapped with the upstream port (non-physical). for details refer to the flexconnect applications [ 9 ] figure 8-1: sof output timing
USB84604 ds60001295c-page 38 ? 2014-2016 microchip technology inc. 8.4 resets the device has the following chip level reset sources: ? power-on reset (por) ? external chip reset (reset_n) ? usb bus reset 8.4.1 power-on reset (por) a power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the device. a timer within the device will assert the internal reset per the specifications listed in section 9.6.1, "power-on configuration strap valid timing," on page 47 . 8.4.2 external chip reset (reset_n) a valid hardware reset is defined as assertion of reset_n, after all power su pplies are within oper ating range, per the specifications in section 9.6.2, "reset and config uration strap timing," on page 48 . while reset is asserted, the device (and its associated external circuitry) ente rs standby mode and c onsumes minimal current. assertion of reset_n causes the following: 1. the phy is disabled and the differential pairs will be in a high-impedance state. 2. all transactions immediately te rminate; no states are saved. 3. all internal registers return to the default state. 4. the external crystal oscillator is halted. 5. the pll is halted. 6. the hsic strobe and data pins are driven low. 8.4.3 usb bus reset in response to the upstream port signaling a rese t to the device, the device performs the following: 1. sets default address to 0. 2. sets configuration to: unconfigured. 3. moves device from suspended to active (if suspended). 4. complies with section 11.10 of the usb 2.0 specification [ 2 ] for behavior after completion of the reset sequence. the host then configures the device in accordance with the usb specification. note: all power supplies must have reach ed the operating levels mandated in section 9.2, "operating condi- tions**," on page 41 , prior to (or coincident wit h) the assertion of reset_n. note: the device does not propagate the upstre am usb reset to downstream devices.
? 2014-2016 microchip technology inc. ds60001295c-page 39 USB84604 8.5 link power management (lpm) the device supports the l0 (on), l1 (sleep), and l2 (s uspend) link power management states per the usb 2.0 link power management addendum. these support ed lpm states offer low transitional la tencies in the tens of microsec- onds versus the much longer latencies of the traditional usb suspend/resume in the tens of milliseconds. the supported lpm states are detailed in ta b l e 8 - 1 . for additional information, refer to the usb 2.0 link power management adden- dum. 8.6 suspend (suspend) when enabled, the suspend signal can be used to indicate that the entire hub has entered the usb suspend state and that vbus current consumption should be re duced in accordance with the usb specification [ 2 ] . selective suspend set by the host on downstream hub ports have no effect on this signal because there is no requirement to reduce current consumption from the upstream vbus. suspend can be used by the system to monitor and dynamically adjust how much current the pmic draws from vbus to charge the bat tery in the system during a u sb session. because it is a level indication, it will assert or negate to reflect the cu rrent status of suspend without any interaction through the smbus. a negation of this signal indicates no level suspend interr upt and device has been configured by the usb host. the full configured current can be drawn from the usb vbus pin on the usb connector for charging - up to 500 ma - depending on descriptor settings. when asserted, this signal indicates a suspend interrupt or that the device has not yet been con- figured by usb host. the curr ent draw can be limited by the system accordi ng to the usb specific ation. the usb spec- ification limits current to 100 ma before conf iguration, and up to 12.5 ma in usb suspend mode. table 8-1: lpm state definitions state description entry/exit time to l0 l2 suspend entry: ~3 ms exit: ~2 ms l1 sleep entry: ~65 s exit: ~100 s l0 fully enabled (on) - note: state change timing is approximate and is measured by change in power consumption. note: system clocks are stopped only in suspend mode or when power is removed from the device.
USB84604 ds60001295c-page 40 ? 2014-2016 microchip technology inc. 9.0 operational characteristics 9.1 absolute maximum ratings* vbat supply voltage ( note 1 ) 0 v to +5.5 v vddcorereg supply voltage ( note 1 ) 0 v to +3.6 v positive voltage on input signal pins, with respect to ground ( note 2 )3.6v negative voltage on input signal pins, with respect to ground ( note 3 )-0.5v positive voltage on xtal1/refclk, with respect to ground vddcr12 positive voltage on hsic signals, with respect to ground 1.32 v positive voltage on usb dp/dm signals, with respect to ground ( note 4 )5.5v storage temperature -55 c to +150 c maximum junction temperature (tjmax) +125 c lead temperature range refer to jedec spec. j-std-020 hbm esd performance jedec class 3a *stresses exceeding those listed in th is section could cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions may af fect device reliability. functional operation of the device at any condition exceeding those indicated in section 9.2, "operating conditions**" , section 9.5, "dc specifications" , or any other applicable section of this specification is not implie d. note, device signals are not 5 volt tolerant unless specified otherwise. note 1: when powering this device from labora tory or system power supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can re sult. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested to use a clamp circuit. note 2: this rating does not apply to the following signals: all usb dm/dp pins, xtal1/refclk, xtal2, and all hsic signals. note 3: this rating does not apply to the hsic signals. note 4: this rating applies only when vdd33 is powered.
? 2014-2016 microchip technology inc. ds60001295c-page 41 USB84604 9.2 operating conditions** vbat supply voltage +3.0 v to +5.5 v vddcorereg supply voltage note 5 power supply rise time note 6 ambient operating temperature in still air (t a ) note 7 **proper operation of the device is guaranteed only within the ranges specifie d in this section. note 5: +1.6 v to +2.0 v when vddcorereg is connected to an external +1.8 v power supply, +3.0 v to +3.6 v when vddcorereg is connected to vdd33. note 6: the power supply rise time requirements vary dependant on the usage of the external reset (reset_n). if reset_n is asserted at po wer-on, the power supply rise time must be 10 ms or less (t rt(max) = 10 ms). if reset_n is not used at power-on (tied high), the po wer supply rise time must be 1 ms or less (t rt(max) = 1 ms). higher voltage supplies must always be at an equal or higher voltage than lower voltage supplies. figure 9-1 and figure 9-2 illustrate the supply rise time requirements. note 7: -40 c to +85 c for automotive version. figure 9-1: single su pply rise time model figure 9-2: dual supply rise time model t 10% 10% 90% voltage t rt t 90% time 100% vbat vss vbat t 10% 10% 90% voltage t rt t 90% time 100% vbat vss vbat 90% 100% 1.8 v vddcorereg
USB84604 ds60001295c-page 42 ? 2014-2016 microchip technology inc. 9.3 package thermal specifications the following thermal parameters are valid for epad = 5.1 x 5.1 mm. 9.4 power consumption this section details the power consumption of the device as measured during various modes of operation. power dis- sipation is determined by temperature, supply voltage, and external source/sink requirements. 9.4.1 operational / unconfigured 9.4.1.1 hsic upstream table 9-1: package thermal parameters parameter symbol c/w velocity (meters/s) thermal resistance junction to ambient ? ja 31 0 thermal resistance junction to ambient ? ja 27 1 thermal resistance junction to top of case ? jc 3.4 thermal resistance junction to board ? jb 17 thermal resistance junction to bottom of case ? jt 0.2 0 thermal resistance junction to bottom of case ? jt 0.4 1 table 9-2: operational/unconfigured power consumption (hsic upstream) typical (ma) maximum (ma) vbat vddcorereg ( note 8 ) vbat vddcorereg ( note 8 ) hs host / 1 hs device 30 40 35 45 hs host / 2 hs devices 50 50 60 55 hs host / 4 hs devices 90 60 100 70 hs host / 1 fs device 15 30 20 40 hs host / 2 fs devices 20 35 20 45 hs host / 4 fs devices 20 40 25 50 unconfigured 10 20 - - note 8: includes vdd12 current. note: the regulators are on. refer to diagram dual supply application in figure 4-1 power connections on page 22 .
? 2014-2016 microchip technology inc. ds60001295c-page 43 USB84604 9.4.1.2 usb upstream 9.4.2 suspend / standby 9.4.2.1 single supply the following tables detail the device power consumption when configured with a single vbat supply and an externally supplied vdd12 for hsic (when applicable). for additional information on power connections, refer to chapter 4.0 power connections on page 21 . usb upstream table 9-3: operational/unconfigured power consumption (usb upstream) typical (ma) maximum (ma) vbat vddcorereg vbat vddcorereg hs host / 1 hs device 30 40 40 45 hs host / 2 hs devices 55 50 65 55 hs host / 4 hs devices 100 65 105 75 hs host / 1 fs device 20 30 25 40 hs host / 2 fs devices 20 40 30 40 hs host / 4 fs devices 25 40 30 45 unconfigured 10 20 - - note: the regulators are on. refer to diagram dual supply application in figure 4-1 power connections on page 22 . table 9-4: single supply suspend/standby power consumption (usb upstream) mode symbol typical @ 25 o c automotive max unit suspend i vbat 320 2000 a standby i vbat 0.4 2.4 a note: typical values measured with vbat = 4.2 v. maximum values measured with vbat = 5.5 v. note: the regulators are on for suspend and off for reset/standby. refer to diagram single supply application in figure 4-1 power connections on page 22 .
USB84604 ds60001295c-page 44 ? 2014-2016 microchip technology inc. hsic upstream 9.4.2.2 dual supply the following tables detail the device power consumpt ion when configured with a dual supply (vbat and 1.8 v vddcorereg) and an externally supplied vdd12 for hsic (w hen applicable). for additional information on power connections, refer to chapter 4.0 power connections on page 21 . usb upstream table 9-5: single supply suspend/standby power consumption (hsic upstream) mode symbol typical @ 25 o c automotive max unit suspend i vbat 120 1500 a i vdd12 5 750 a standby i vbat 0.2 2.2 a note: typical values measured with vbat = 4.2 v, vdd1 2 = 1.2 v. maximum values measured with vbat = 5.5 v, vdd12 = 1.32 v. note: the regulators are on for suspend and off for reset/standby. refer to diagram single supply application in figure 4-1 power connections on page 22 . table 9-6: dual supply suspend/standby po wer consumption (usb upstream) mode symbol typical @ 25 o c automotive max unit suspend i vddcorereg 80 1350 a i vbat 230 400 a standby i vddcorereg 0.1 2.5 a i vbat 0.4 2.5 a note: typical values measured with vbat = 4.2 v, vddc orereg = 1.8 v. maximum values measured with vbat = 5.5 v, vddcorereg = 2.0 v. note: the regulators are on for suspend and off for reset/standby. refer to diagram dual supply application in figure 4-1 power connections on page 22 .
? 2014-2016 microchip technology inc. ds60001295c-page 45 USB84604 hsic upstream table 9-7: dual supply suspend/standby po wer consumption (usb upstream) mode symbol typical @ 25 o c automotive max unit suspend i vddcorereg 90 1300 a i vbat 30 750 a i vdd12 5.5 1100 a standby i vddcorereg 0.1 2.5 a i vbat 0.4 2.5 a note: typical values measured with vbat = 4.2 v, v ddcorereg = 1.8 v, vdd12 = 1.2 v. maximum values measured with vbat = 5.5 v, vddcorereg = 2.0 v, vdd12 = 1.32 v. note: the regulators are on for suspend and off for reset/standby. refer to diagram dual supply application in figure 4-1 power connections on page 22 .
USB84604 ds60001295c-page 46 ? 2014-2016 microchip technology inc. 9.5 dc specifications table 9-8: dc electrical characteristics parameter symbol min typ max units notes is type input buffer low input level high input level v il v ih -0.3 2.0 0.8 3.6 v v i_rst type input buffer low input level high input level v il v ih -0.3 1.25 0.4 3.6 v v i_smb type input buffer low input level high input level v il v ih -0.3 1.25 0.35 3.6 v v o6 type buffers low output level high output level v ol v oh vdd33 - 0.4 0.4 v v i ol = 6 ma (default) i oh = -6 ma see note 9 od6 type buffer low output level v ol 0.4 v i ol = 6 ma (default) see note 9 o8 type buffers low output level high output level v ol v oh vdd33 - 0.4 0.4 v v i ol = 8 ma i oh = -8 ma od8 type buffer low output level v ol 0.4 v i ol = 8 ma hsic type buffers low input level high input level low output level high output level v il v ih v ol v oh -0.3 0.65*vdd12 0.75*vdd12 0.35*vdd12 vdd12+0.3 0.25*vdd12 v v v v
? 2014-2016 microchip technology inc. ds60001295c-page 47 USB84604 9.6 ac specifications this section details the various ac timing specifications of the device. 9.6.1 power-on configuration strap valid timing figure 9-3 illustrates the configuration strap timing requirements , in relation to power-on, for applications where reset_n is not used at power- on. the operational levels (v opp ) for the external power supplies are detailed in section 9.2, "operating conditions**," on page 41 . iclk type buffer (xtal1/refclk input) low input level high input level v il v ih -0.3 0.8 0.35 3.6 v v note 10 note 9: o6, od6: the pad strength can be increased to 12 ma for spi bridging applications. note 10: xtal2 can optionally be driven from a 24 mhz single-ended clock oscillator (refclk). note: for reset_n configurat ion strap timing requ irements, refer to section 9.6.2, "reset and configuration strap timing," on page 48 . figure 9-3: power-on config uration strap valid timing table 9-9: power-on config uration strap valid timing symbol description min typ max units t csh configuration strap hold after external power supplies at operational levels 1ms table 9-8: dc electrical characteristics (continued) parameter symbol min typ max units notes all external power supplies v opp configuration straps t csh
USB84604 ds60001295c-page 48 ? 2014-2016 microchip technology inc. 9.6.2 reset and configuration strap timing figure 9-4 illustrates the reset_n timing requirements and its rela tion to the configuration st rap signals. assertion of reset_n is not a requirement. howeve r, if used, it must be asserted fo r the minimum period specified. refer to section 8.4, "resets," on page 38 for additional information on resets. refer to section 6.3, "device configu- ration straps," on page 29 for additional information on configuration straps. 9.6.3 usb timing all device usb signals conform to the voltage, power, and timing characteristics/specifications as set forth in the uni- versal serial bus specification . please refer to the universal serial bus specification , revision 2.0, available at http:// www.usb.org [ 2 ] . 9.6.4 hsic timing all device hsic signals conform to the voltage, power, and timing characteri stics/specifications as set forth in the high- speed inter-chip usb electrical specification . please refer to the high-speed inter-chip usb electrical specification , version 1.0, available at http://www.usb.org [ 4 ] . 9.6.5 smbus timing all device smbus signals conform to the voltage, power, and ti ming characteristics/specificat ions as set forth in the sys- tem management bus specification . please refer to the system management bus specification , version 1.0, available at http://smbus/org/specs [ 6 ] . 9.6.6 i 2 c timing all device i 2 c signals conform to the 100 khz standard mode (sm) voltage, power, and timing characteristics/specifica- tions as set forth in the i 2 c-bus specification . please refer to the i 2 c-bus specification , available at http://www.nxp.com [ 5 ] . figure 9-4: reset_n conf iguration strap timing table 9-10: reset_n configuration strap timing symbol description min typ max units t rstia reset_n input assertion time 5 s t csh configuration strap hold af ter reset_n deassertion 1 ms reset_n configuration straps t rstia t csh
? 2014-2016 microchip technology inc. ds60001295c-page 49 USB84604 9.6.7 spi timing the following specifies the spi timing requirements for the device. figure 9-5: spi timing note: the spi can be configured for 30 mhz or 60 mhz operation via the spi_spd_sel configuration strap. 30 mhz operation timing values are shown in ta b l e 9 - 11 . 60 mhz operation timing values are shown in table 9-12 . table 9-11: spi timing values (30 mhz operation) symbol description min typ max units t fc clock frequency 30 mhz t ceh chip enable (spi_ce_en) high time 100 ns t clq clock to input data 13 ns t dh input data hold time 0 ns t os output setup time 5 ns t oh output hold time 5 ns t ov clock to output valid 4 ns t cel chip enable (spi_ce_en) low to first clock 12 ns t ceh last clock to chip enable (spi_ce_en) high 12 ns spi_clk spi_di spi_do spi_ce_n t cel t fc t clq t ceh t dh t oh t os t ov t oh
USB84604 ds60001295c-page 50 ? 2014-2016 microchip technology inc. table 9-12: spi timing values (60 mhz operation) symbol description min typ max units t fc clock frequency 60 mhz t ceh chip enable (spi_ce_en) high time 50 ns t clq clock to input data 9 ns t dh input data hold time 0 ns t os output setup time 5 ns t oh output hold time 5 ns t ov clock to output valid 4 ns t cel chip enable (spi_ce_en) low to first clock 12 ns t ceh last clock to chip enable (spi_ce_en) high 12 ns
? 2014-2016 microchip technology inc. ds60001295c-page 51 USB84604 9.7 clock specifications the device can accept either a 24 mhz crystal or a 24 mhz si ngle-ended clock oscillator inpu t. if the single-ended clock oscillator method is implemented, xta l1 should be left unconnected and refclk should be driven with a clock that adheres to the specifications outlined in section 9.7.2, "external reference clock (refclk)" . 9.7.1 oscillator/crystal it is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (xtal1i/xtal2). see table 9-13 for the recommended crystal specifications. 9.7.2 external reference clock (refclk) the following input clock specifications are suggested: ? 50% duty cycle ? 10% ? 24 mhz ? 350 ppm table 9-13: crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 24.000 - mhz total allowable ppm budget - - +/-350 ppm operating temperature range note 11 - note 12 c note 11: -40 c for automotive version. note 12: +85 c for automotive version. note: the external clock is recommended to conform to th e signalling levels designated in the jedec specifica- tion on 1.2 v cmos logic although maximum values of 3.6 v are stated in section 9.1, "absolute maxi- mum ratings*," on page 40 and in table 9-8, ?dc electrical characteristics,? on page 46 . xtal2 should be treated as a no connect when an external clock is supplied.
USB84604 ds60001295c-page 52 ? 2014-2016 microchip technology inc. 10.0 package outline figure 10-1: USB84604 48-pin qfn package drawing b a 0.10 c 0.10 c 0.10 c a b 0.05 c (datum b) (datum a) c seating plane 1 2 n 2x top view side view microchip technology drawing c04-363a sheet 1 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: note 1 1 2 n 0.10 c 0.08 c bottom view 0.10 c a b a1 a a2 2x 0.10 c 4x see detail b 4x p 4x p 48x l see detail a 0.10 c a b 48-lead plastic quad flat, no lead package (5e) - 7x7 mm body [qfn] with 5.1x5.1 mm exposed pad; punch singulated, 0. 40 mm dimpled terminals d e1 e d1 48x , 48x b e e 2 d2 e2 nx k (a3)
? 2014-2016 microchip technology inc. ds60001295c-page 53 USB84604 figure 10-1: USB84604 48-pin qfn package drawing microchip technology drawing c04-363a sheet 2 of 2 number of terminals overall height terminal width overall width overall length terminal length exposed pad width exposed pad length terminal thickness pitch standoff units dimension limits a1 a b d e2 d2 (a3) e l e n 0.50 bsc 0.20 ref 5.00 0.30 0.20 0.80 0.00 0.25 0.40 5.10 0.85 0.01 7.00 bsc millimeters min nom 48 5.20 0.50 0.30 0.90 0.05 max t - 0 12 ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2. 3. notes: pin 1 visual index feature may vary, but must be located within the hatched area. package is punch singulated dimensioning and tolerancing per asme y14.5m mold draft angle a2 0.60 0.65 0.70 e1 6.75 bsc d1 mold cap height molded top width molded top length terminal-to-exposed-pad k 0.20 - - 7.00 bsc 6.75 bsc b b1 l2 detail a l l1 detail b terminal dimple width b1 0.10 0.15 0.20 terminal dimple length (side) terminal dimple length (bottom) l1 0.05 0.15 0.25 l2 0.05 0.10 0.15 corner chamfer p 0.24 0.42 0.60 5.00 5.10 5.20 terminal dimples for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 48-lead plastic quad flat, no lead package (5e) - 7x7 mm body [qfn] with 5.1x5.1 mm exposed pad; punch singulated, 0.40 mm dimpled terminals
USB84604 ds60001295c-page 54 ? 2014-2016 microchip technology inc. figure 10-1: USB84604 48-pin qfn package drawing recommended land pattern dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch y2 x2 5.20 5.20 millimeters 0.50 bsc min e max 6.90 contact pad length (x48) contact pad width (x48) y1 x1 0.85 0.30 bsc: basic dimension. theoretically exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m microchip technology drawing c04-2363a nom silk screen 1 2 48 c1 c2 e x1 y1 g1 y2 x2 c1 contact pad spacing 6.90 contact pad to center pad (x44) g1 0.20 thermal via diameter v thermal via pitch ev 0.33 1.20 ?v ev ev for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 48-lead plastic quad flat, no lead package (5e) - 7x7 mm body [qfn] with 5.1x5.1 mm exposed pad; punch singulated, 0.40 mm dimpled terminals
? 2014-2016 microchip technology inc. ds60001295c-page 55 USB84604 appendix a: data sheet revision history revision level section/ figure/entry correction ds60001295c cover page new added in highlights: device functionality and configuration for usb host/slave swap- ping is also provided by external spi flash new added in target applications: smart phones requiring host and device modes figure 2-1 package designators added below the figure. figure 5-1 corrected section 6.4 added new section spi external flash section 9.1 added value for maximum junction temperature section 9.3 added new section package thermal specifications chapter 10.0 package information adapted. product identification system removed reel size. ds60001295b initial release
USB84604 ds60001295c-page 56 ? 2014-2016 microchip technology inc. appendix b: term s and acronyms the following is a list of general terms and acronyms used throughout this document: acronym description 2dfu device firmware upgrade eop end of packet ep endpoint fs full-speed gpio general purpose i/o (that is input/output to/from the device) hmi human machine interface hs hi-speed hsos high speed over sampling hsic high-speed inter-chip hub controller it is an internal part of the chip. it adds advanced functionality (e .g., control of bridging, gpio etc) to the (refer to page 5 ). i 2 c ? inter-integrated circuit ls low-speed mtt multi-transaction translator ocs over-current sense otp one time programmable pcb printed circuit board pcs physical coding sublayer phy physical layer pio general purpose i/o (that is internal to the device) por power on reset sdk software development kit smbus system management bus spi serial peripheral interface sqfn square quad flat no-lead tt transaction translator uch usb controller hub usb controller hub usb hub that has an embedded microcontroller to enable enhanced features. uuid universally unique identification vsm vendor specific messaging
? 2014-2016 microchip technology inc. ds60001295c-page 57 USB84604 appendix c: references [1] unicode utf-16le for string descriptors usb engineering change notice, december 29th, 2004, usb implementers forum, inc. http://www.usb.org [2] universal serial bus specification , revision 2.0, april 27th, 2000, usb implementers forum, inc. http://www.usb.org [3] battery charging specification , revision 1.2, dec. 07, 2010, usb implementers forum, inc. http://www.usb.org [4] high-speed inter-chip usb electrical specification , version 1.0, sept. 23, 2007, usb implementers forum, inc. http://www.usb.org [5] i2c-bus specification , version 1.1, nxp (formerly a division of philips) http://www.nxp.com [6] system management bus specification , version 1.0, http://smbus/org/specs [7] an 26.18 smbus slave interface for the usb253x/ usb3x13/usb46x4 this application note is also valid for USB84604. http://www.microchip.com [8] an 26.19 usb battery charging with t he microchip/smsc usb2534 hub controller http://www.microchip.com [9] an1580, an1627, an1700, flexconnect applications http://www.microchip.com
USB84604 ds60001295c-page 58 ? 2014-2016 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support
? 2014-2016 microchip technology inc. ds60001295c-page 59 USB84604 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: USB84604 temperature range: a= -40 ? c to +85 ? c package: f = qfn dimple package (48-pin) tape and reel option: blank = standard packaging (tray) t = tape and reel (1) pattern b = product version rom/firmware 001070 = rom/firmware combination 001080 = rom/firmware combination version vxx =automotive designator examples: a) USB84604af-b-001080-v03 -40 ? c to + 85c, qfn dimple package (48-pin), tray, b, 001080 (hub controller disabled) v03 b) USB84604aft-b-001080-v03 -40c to + 85c, qfn dimple package (48-pin), tape & reel, b, 001080 (hub controller enabled) v03 note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the dev ice package. check with your microchip sa les office for package availability with the tape and reel option. . part no. [x] x range device (1) - option temperature package [x] tape and reel x product - version rom/ xxxxxx firmware - version vxx
? 2014-2016 microchip technology inc. ds60001295c-page 60 quality management system certified by dnv == iso/ts 16949 == note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outs ide the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconducto r manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. information contained in this publication re garding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with y our specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims al l liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and t he buyer agrees to defend, i ndemnify and hold harmless microchip from any and all damages, claims, suit s, or expenses resulting from su ch use. no licenses are conveyed, implic- itly or otherwise, under any microchip intellect ual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip l ogo, anyrate, dspic, flashflex, flexpw r, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersyn ch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered tradem arks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, body com, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit se rial programming, icsp, inter-c hip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, vari sense, viewspan, wiperlock, wireless dna, and zena are trademarks of mi crochip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2014-2016, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn: 978-1-5224-0641-9 microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds60001295c-page 61 ? 2014-2016 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-695-1980 fax: 905-695-2078 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - guangzhou tel: 86-20-8755-8029 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - karlsruhe tel: 49-721-625370 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 06/23/16

▲Up To Search▲

Price & Availability of USB84604

	To Download USB84604 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .